ASIC Engineer, Emulation
Meta

Job Info

Meta is hiring ASIC Emulation Engineers within our Infrastructure organization. We are looking for individuals with experience in HW emulation and prototyping required to build System on Chip (SoC) and IP for data center applications.

ASIC Engineer, Emulation Responsibilities:

• Develop emulation testbenches in System Verilog and/or C/C++.
• Deliver emulation and prototyping models from RTL on industry standard emulation and prototyping platforms.
• Build and execute emulation test plan to ensure quality of the models and assist pre-silicon validation.
• Drive emulation methodologies for HW verification and SW development.
• Develop emulation tools, workflows and infrastructure in collaboration with RTL, verification, validation and SW teams for productivity during debug, runtime, and data analysis of results from emulation runs.
• Bring up and debug PCIe, DDR and generic SOC interfaces.
• Develop emulation validation components for validation efficiency in testing, debug and automation.
• Develop and drive improvements using the latest emulation technology from industry.
• Partner with vendors to debug issues and deploy new emulation capabilities.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 3+ Years of experience with EDA tools and scripting languages used to build tools and flows for complex emulation environments.
• Experience with current emulation technologies and methods, example simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, hybrid methods.

Preferred Qualifications:

• Track record of 'first-pass success' in ASIC where emulation is one of the key validation tools.
• Understanding of compilation and build flow with experience building images from scratch with necessary design modifications to adapt to emulation.
• Experience with verification, SoCs or similar designs.
• Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip system) with an understanding of trade-offs between performance and ease of debug.
• Experience managing multiple design releases and working with cross functional teams to support and debug customer issues.
• Experience with SystemVerilog and C++ to model RTL components and transactors.
• Experience with post-silicon bring up, debug and reproducing issues on emulator.
• Experience with Palladium, Protium, or Zebu tools.
• Experience with Python and TCL scripting languages.
• Experience interfacing with the design, verification, validation and software development teams and understand their needs from an emulation perspective.

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